1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced stability, microelectronic devices within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are fabricated employing microelectronic devices as active and passive elements which are connected and interconnected while employing patterned microelectronic conductor layers to form electrical circuits formed within, upon and/or over microelectronic substrates.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become common in the art of microelectronic fabrication to employ interposed between and passivating microelectronic devices and patterned microelectronic conductor layers within microelectronic fabrications dielectric materials with enhanced gap filling properties and with lower dielectric constant properties. Dielectric materials with enhanced gap filling properties are desirable interposed between and passivating microelectronic devices and patterned microelectronic conductor layers within microelectronic fabrications since there may then be avoided interposed between and passivating microelectronic devices and patterned microelectronic conductor layers dielectric layers having formed therein voids. Similarly, dielectric materials with lower dielectric constant properties (i.e., dielectric constants less than about 3.7 and more preferably from about 3.6 to about 3.8, in comparison with conventional dielectric materials, such as silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials having dielectric constants of generally greater than about 4.3 and more typically from about 4.0 to about 4.5) are desirable interposed between and passivating microelectronic devices and patterned microelectronic conductor layers within microelectronic fabrications since there is then typically fabricated microelectronic fabrications with enhanced microelectronic fabrication speed, attenuated patterned microelectronic conductor layer cross-talk and attenuated patterned microelectronic conductor layer parasitic capacitance.
While dielectric materials with enhanced gap filling properties and lower dielectric constant properties are thus desirable in the art of microelectronic fabrication, dielectric materials with enhanced gap filling properties and/or lower dielectric constant properties are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is often observed when fabricating microelectronic fabrications having formed therein semiconductor microelectronic devices, such as but not limited to metal oxide semiconductor field effect transistor (MOSFET) devices, that there is observed instability in various semiconductor microelectronic device performance parameters as a function of the nature of a dielectric material with enhanced gap filling properties and/or lower dielectric constant properties which is employed to either directly or indirectly passivate the semiconductor microelectronic devices.
It is thus towards the goal of forming within the art of microelectronic fabrication microelectronic fabrications having formed therein microelectronic devices either directly or indirectly passivated with various dielectric materials, with enhanced stability of the microelectronic devices, that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming stabilized microelectronic devices and stabilized microelectronic structures within microelectronic fabrications.
For example, Levinstein et al., in U.S. Pat. No. 4,151,007, disclose a method for stabilizing the threshold voltage and the flat band voltage of a metal oxide semiconductor field effect transistor (MOSFET) device employed within a semiconductor integrated circuit microelectronic fabrication. The method employs, after the last thermal process to which the metal oxide semiconductor field effect transistor (MOSFET) device is exposed at greater than about 600 degrees centigrade a thermal annealing of the metal oxide semiconductor field effect transistor (MOSFET) device at a temperature of from about 650 to about 950 degrees centigrade in a pure hydrogen environment.
In addition, Hickox et al., in U.S. Pat. No. 4,154,873, disclose a method for increasing a field inversion voltage of a field oxide layer with respect to a silicon semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication, while simultaneously decreasing a leakage current of the field oxide layer with respect to the silicon semiconductor substrate employed within the semiconductor integrated circuit microelectronic fabrication. The method employs, when forming the field oxide layer within the semiconductor integrated circuit microelectronic fabrication: (1) a thermal annealing reoxidation of a field oxide layer while employing an oxidizing gas at a temperature of from about 600 to about 950 degrees centigrade to thus form a reoxidized field oxide layer having an increased density of charge trapped within the bulk of the reoxidized field oxide layer, followed by; (2) a thermal annealing of the reoxidized field oxide layer within a hydrogen annealing environment at a temperature of from about 300 to about 500 degrees centigrade to form a hydrogen annealed reoxidized field oxide layer having a reduced surface charge density in comparison with the reoxidized field oxide layer, while not substantially decreasing the bulk density of charge trapped within the hydrogen annealed reoxidized field oxide layer.
Further, Guldi, in U.S. Pat. No. 5,334,556, discloses a method for forming within a metal oxide semiconductor (MOS) device, such as a metal oxide semiconductor field effect transistor (MOSFET) device, an oxide layer with enhanced dielectric integrity and stability. The method employs incorporating into an otherwise inert gas annealing environment employed for annealing a semiconductor portion of the metal oxide semiconductor (MOS) device, such as a pair of source/drain regions within a semiconductor substrate employed within the metal oxide semiconductor field effect transistor (MOSFET) device, a minor component of an oxidizing gas, such as but not limited to oxygen, hydrogen chloride, nitrogen trifluoride or fluorine, at a point in the thermal annealing method other than the highest temperature plateau employed within the thermal annealing method.
Still further Liu et al., in U.S. Pat. No. 5,646,057, disclose a method for improving the performance characteristics of a metal oxide semiconductor (MOS) device formed within a microelectronic fabrication subsequent to annealing the microelectronic fabrication while employing a rapid thermal annealing method which generally deteriorates the performance of the metal oxide semiconductor (MOS) device formed within the microelectronic fabrication. The method employs subsequent to the rapid thermal annealing of the microelectronic fabrication a conventional thermal annealing of the microelectronic fabrication in a hydrogen annealing environment at a temperature of at least about 430 degrees centigrade.
Finally, Lane et al., in U.S. Pat. No. 5,895,274, disclose a hydrogen thermal annealing method for repairing integrated circuit fabrication induced damage to integrated circuit microelectronic fabrication devices within integrated circuit microelectronic fabrications, where the hydrogen thermal annealing method minimizing a thermal exposure time and a thermal exposure temperature employed within the hydrogen thermal annealing method. The hydrogen thermal annealing method realizes the foregoing objects by employing within the hydrogen thermal annealing method a super-ambient pressure to compensate for the minimized thermal exposure time and the minimized thermal exposure temperature.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for fabricating within microelectronic fabrications microelectronic devices with enhanced stability.
It is towards the foregoing object that the present invention is directed.